AHB and OCP
Behavioral Synthesis of Asynchronous Circuits
Speed Optimization of a FPGA Based Modified Viterbi Decoder
Implementation of I2C Interface
A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique
Clamping Virtual Supply Voltage of Power Gated Circuits for Active Leakage Reduction and Gate Oxide Reliability
FPGA Based Power Efficient Channelizer for Software Defined Radio
VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication
Operation Improvement of Indoor Robot
Design and Implementation of an ON-Chip Permutation Network for Multiprocessor System On-Chip
A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
DMA Controller (Direct Memory Access ) Using VHDL/VLSI
Reconfigurable FFT Using CORDIC Based Architecture for MIMI-OFDM Receivers
Spurious Power Suppression Technique for Multimedia/DSP Applications
Efficiency of BCH Codes in Digital Image Watermarking
Dual Data Rate SD RAM Controller
Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL
Design of a Practical Nanometer Scale Redundant via Aware Standard Cell Library for Improved Redundant via 1 Insertion Rate
A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture
A Framework for Correction of Multi-Bit Soft Errors
Viterbi-Based Efficient Test Data Compression
Implementation of FFT/IFFT Blocks for OFDM
Wavelet Based Image Compression by VLSI Progressive Coding
VLSI Implementation of Fully Pipelined Multiplier Less 2d DCT/IDCT Architecture for Jpeg